A considerable process step of semiconductor process technology is the so-called pattern transfer and/or the transfer of a pattern onto a medium to be patterned, for which purpose lithography is used. In general, a distinction is made between optical lithography or electron-beam lithography and ion-projection lithography. In case of the optical lithography, the generation of the pattern or the transfer of the pattern to a substrate to be patterned is achieved by using a mask that is respectively patterned to generate the required pattern on the substrate during exposure. For ion-projection lithography, masks can also be used for pattern imaging. Using electron-beam lithography, the required pattern can be directly written onto a respective substrate without the use of a mask. The above lithography processes can also be combined in any way, so that, for instance, certain patterns are produced by optical lithography and other patterns are written directly onto the already prestructured wafer and/or substrate using electron-beam lithography.
Developments in the semiconductor technology provide increasingly finer chip patterns and circuit complexity. The aforementioned pattern transfer is a critical process step for the production of complex semiconductor process technology patterns. In order to obtain the required pattern accuracy during the pattern transfer procedure, starting from the chip layout up to the etched wafer pattern, process influences causing pattern distortion and thus yield losses must be considered and/or compensated for.
Depending on the used lithography process, various correction methods are used to correct the pattern distortion induced by the pattern transfer procedure.
In case of the optical and ion-projection lithography, using masks as projection template, imaging distortions and pattern-distorting process influences are, for instance, corrected by a geometric optimisation of the chip layout information at mask level.
In the optical lithography, this correction method is referred to as "optical proximity correction" and is, for instance, described in the articles "Evaluation of a fast and flexible OPC package: OPTISSIMO," W. Maurer, T. Waas, H. Eisenmann, Photomask Technology and Management, SPIE 2884, p. 412 ff., 1996, "Application of a simple resist model to fast optical proximity correction," C. Dolainsky, W. Maurer, Optical Microlithography X, SPIE 3051, p. 774 ff., 1997 and "Evaluation of resist models for fast optical proximity correction," C. Dolainsky, W. Maurer, T. Waas in 17.sup.th BACUS Symposium on Photomask Tech, Proc., SPIE 3236, page 202 ff., 1998.
To increase pattern fidelity during electron-beam lithography, the electron-beam energy or the dose value can be modulated to achieve the required pattern fidelity. The correction of the proximity effect during electron-beam lithography is, for instance, described in DE4317899C2 and in article "PROXECCO--Proximity effect correction by convolution," H. Eisenmann, T. Waas, H. Hartmann, J. Vac. Sci. Technol. B(116), Nov./Dec. 1993, pages 2741-2745.
With reference to FIG. 6, a known prior art procedure for maintaining the required pattern accuracy during a pattern transfer process as part of the production of semiconductor process technology pattern is described below.
In a first process stage S600, design information representing the required information for a specified chip design, is provided. Based on this design information, a layout of the required chip pattern is generated, which is then processed further in step S602. The example shown in FIG. 6 relates to a production procedure which, using an electron beam, writes directly onto a wafer or a substrate. In step S602 a proximity correction using the steps described in the above listed prior art publications, is now carried out in addition to the further processing. In the described example, an electron-beam proximity correction can be carried out via the dose, i.e., for certain areas of the layout certain dose values are set for the electron beam to ensure pattern accuracy and to prevent pattern distortion. In step S602 a correction of the process influences can be carried out in addition or instead of the dose correction via the layout geometry, by, for instance, certain edges of the layout being displaced to prevent pattern distortion in order to compensate for the distortion generated by the production procedure. Based on the carried out corrections, the layout is revised in step 602, so that after step S602a corrected layout in which the fault correction has been considered, is achieved. This corrected layout is used in step 604 to control the electron-beam exposure which in this case, for instance, exposes a resist, so that a resist image is formed on the wafer to be patterned after step S604. During the following process steps S606, the final pattern of the wafer is generated by, i.e., the development of the resist and additional etching steps, until the final result is the patterned wafer. To explain the layout change in step S602, one example, showing in which way a predetermined layout is changed by the correction, is described below with reference to FIG. 7 and 8.
With reference to FIG. 7, an example in which the proximity correction is achieved by setting the dose values for an electron beam during exposure, is described below. FIG. 7a shows layout 700 as an example. The layout contains four rectangles 702, of which two are separated by a vertical gap 704 and thin lines 706 are arranged between the two rectangle pairs. The layout 700 shown in FIG. 7a is defined by design information provided in step S600 and the proximity correction in step S602 results in a corrected layout 710 as shown in FIG. 7b. As clearly apparent from a comparison between FIG. 7a and 7b, the correction causes the rectangles 702 shown in FIG. 7a to now be formed by several smaller rectangles 712, with the same applying to the lines 702. The correction in step S602 causes different dose values for the electron beam exposure to be assigned to the respective rectangles 712 of the layout pattern shown in FIG. 7b in order to compensate for the pattern distortion during pattern transfer.
As clearly apparent from a comparison between FIG. 7a and 7b, the "simple" layout (see FIG. 7a) has already in this example changed to a very complex layout (see FIG. 7b), which compared to the original layout can only be written to with a considerably higher information quantity.
With reference to FIG. 8, a further example will now be described in which, contrary to FIG. 7, not the layout for writing directly to the substrate but the layout for producing a mask for optical lithography, is corrected.
FIG. 8a, shows the layout 800, defined by design information, which is made up of a simple pattern of several conductor lines 802. As a result of the above described optical proximity correction, a mask pattern 804, shown in FIG. 8b, in which critical points 806 were corrected, is produced. When looking, for instance, only at the conductor line at the very right of FIG. 8a and comparing it with the corrected conductor line shown in FIG. 8b, it is apparent that as a result of the proximity correction the information quantity required for writing the mask layout has considerably increased. Whilst the structure shown in FIG. 8a could still be written by simple data sets, a comparison with FIG. 8b shows that considerably more information is required for writing this design than for FIG. 8a.
The optimal layout geometry and/or dose distribution for correcting process influences, described with reference to the above example and determined by complex calculations, generates the described geometric layout information change. Consequently, the initial information for the mask production or for the electron-beam lithography increases in complexity and in order of magnitude.
Known prior art fault correction solutions therefore have the disadvantage that, due to the carried out correction measures, the layout is changed considerably in its form and/or size and, in particular, in the information quantity. This will be disadvantageous for gigabit and terabit layout sizes expected in future, as due to the implementation of the corrective measures, direct geometrical changes and due to the associated increase in layout complexity and information quantity, such layouts can no longer be sensibly used.
Another disadvantage of this solution is that the corrective measure is carried out individually or independently from the pattern generating procedure or the device used for this purpose, so that no ideal adaptation to the system carrying out the patterning, such as an electron-beam system, is possible. A further disadvantage is that the "double implementation, i.e., the provision of the layout and then the implementation of the correction, the combination of layout and correction for generating a corrected layout and the subsequent transfer to the pattern generating system, limits the improvement of the achievable pattern accuracy in the final pattern on the wafer. A further disadvantage is that in an attempt to compensate for various process influences, the layout complexity and information quantity already increased by a first correction measure, is again increased in orders of magnitudes if further process influences are to be corrected.
Another disadvantage, ie., that the transfer of the layout information in the process is extremely difficult due to the changing circuit complexity, is apparent.